/**
 * MIT License
 * 
 * Copyright (c) 2024 - present @ ebraid
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */


#include <config.h>
#include <types.h>
#include <kernel/initcall.h>
#include <kernel/syslog.h>
#include <drivers/gpio.h>
#include <drivers/irq.h>
#include <suniv.h>
#include <irqnum.h>
#include <io.h>
#include <stdio.h>


#define   INTC_VECTOR_OFFSET               (0x00)
#define   INTC_BASE_ADDR_OFFSET            (0x04)
#define   INTC_NMI_CTRL_OFFSET             (0x0C)
#define   INTC_PEND0_OFFSET                (0x10)
#define   INTC_PEND1_OFFSET                (0x14)
#define   INTC_ENABLE0_OFFSET              (0x20)
#define   INTC_ENABLE1_OFFSET              (0x24)
#define   INTC_MASK0_OFFSET                (0x30)
#define   INTC_MASK1_OFFSET                (0x34)
#define   INTC_RESP0_OFFSET                (0x40)
#define   INTC_RESP1_OFFSET                (0x44)
#define   INTC_FORCE0_OFFSET               (0x50)
#define   INTC_FORCE1_OFFSET               (0x54)
#define   INTC_PRIORITY0_OFFSET            (0x60)
#define   INTC_PRIORITY1_OFFSET            (0x64)
#define   INTC_PRIORITY2_OFFSET            (0x68)
#define   INTC_PRIORITY3_OFFSET            (0x6C)


// port = 0, 1, 2 (GPIOD, GPIOE, GPIOF)
#define   INT_STAX_REG(port)               (0x1C20A00 + (port) * 0x20 + 0x14)


static irq_handler_t eb_irq_table[CONFIG_IRQTABLE_SIZE] = {0};
static void* eb_irq_table_arg[CONFIG_IRQTABLE_SIZE] = {0};


/* IRQ Entry Point */
void irq_handler(void) 
{
    uint32_t irq_num = read32(INTC_REG_BASE) >> 2;
    
    // clear all pending bits for the current GPIO IRQ
    write32(INT_STAX_REG(irq_num - IOD_IRQNUM), 0xFFFFFFFF);

    if(eb_irq_table[irq_num] != NULL) {
        eb_irq_table[irq_num](eb_irq_table_arg[irq_num]);
    }
    else {
        irq_disable(irq_num);
    }
}


static int irq_init(void)
{
    /* Disable all interrupts */
    write32(INTC_REG_BASE + INTC_ENABLE0_OFFSET, 0);
    write32(INTC_REG_BASE + INTC_ENABLE1_OFFSET, 0);

    /* Set vector base */
    write32(INTC_REG_BASE + INTC_BASE_ADDR_OFFSET, 0); // Set offset to 0

    return 0;
}


int irq_request(uint32_t irq, irq_handler_t handler, void *data)
{
    if(eb_irq_table[irq] == NULL) {
        eb_irq_table[irq] =  handler;
        eb_irq_table_arg[irq] = data;
        return 0;
    }
    else {
        return -1;
    }
}


void irq_free(uint32_t irq)
{
    eb_irq_table[irq] = NULL;
}


void irq_enable(uint32_t irq)
{
    size_t intc_en0 = read32(INTC_REG_BASE + INTC_ENABLE0_OFFSET);
    size_t intc_en1 = read32(INTC_REG_BASE + INTC_ENABLE1_OFFSET);

    if(irq < 32) {
        intc_en0 |= BIT(irq);
        write32(INTC_REG_BASE + INTC_ENABLE0_OFFSET, intc_en0);
    }
    else {
        intc_en1 |= BIT(irq - 32);
        write32(INTC_REG_BASE + INTC_ENABLE1_OFFSET, intc_en1);
    }
}


void irq_disable(uint32_t irq)
{
    size_t intc_en0 = read32(INTC_REG_BASE + INTC_ENABLE0_OFFSET);
    size_t intc_en1 = read32(INTC_REG_BASE + INTC_ENABLE1_OFFSET);

    if(irq < 32) {
        intc_en0 &= ~(BIT(irq));
        write32(INTC_REG_BASE + INTC_ENABLE0_OFFSET, intc_en0);
    }
    else {
        intc_en1 &= ~(BIT(irq - 32));
        write32(INTC_REG_BASE + INTC_ENABLE1_OFFSET, intc_en1);
    }
}


void irq_clear_flag(unsigned long irq)
{
    // clear '1' bit pending bits for the current GPIO IRQ
    write32(INT_STAX_REG(irq - IOD_IRQNUM), 0xFFFFFFFF);
}


core_initcall(irq_init);
